Encoder having an analog input signal centering arrangement



Feb. 10, 1970 M. E. GABRIEL 3,495,238

ENcoDER HAVING AN ANALOG INPUT SIGNAL CENTERING ANRANGEMENT Filed Nov. 9, 1967 2 Sheets-Sheet l MALCOLM f. @ABR/f Agent Feb. 10, 1970 M. E. GABRIEL 3,495,238

ENCODER HAVING AN ANALOG INPUT SIGNAL CENTERING ARRANGEMENT Filed Nov. 9, 1967 2 Sheets-Sheet 2 5f. @gi

Inventar' y MALCOLM E. GABR/EL By WLM Agent 3,495,238 ENCODER HAVING AN ANALOG INPUT SIGNAL CENTEIRING ARRANGEMENT Malcolm Edward Gabriel, Basildon, Essex, England, as-

signor to International Standard Electric Corporation, New York, NgY., a corporation of Delaware Filed Nov. 9, 1967, Ser. No. 681,622 Claims priority, application Great Britain, Nov. 22, 1966,

, lint. Cl. 608e 19/00 ILS. Cl. 340-348 Claims Ans'rniicr or 'ran nrscrosonn BACKGROUND OF THE INVENTION This invention relates to encoders for encoding analog signals into a ysymmetrical binary code and in particular to an automatic control circuit for such encoders.

The advantages of using the symmetricalpbinary code for the encoding of speech signals in Pulse Code Modulation (PCM) telecommunication systems are'well known. In this code the first digit indicates the polarity of the analog signal to be encoded, the remaining -digits of the code indicating the amplitude of the signal. It is also known to be advantageous to give encodersia non-linear characteristic and to adjust the size of the quantizing steps in accordance with the amplitude of the analog signal to be coded.

In such coders it is important that the zero of the input signal should 'coincide with the center of tlie code structure if maximum companding advantage is to be derived.

The centering of the input signal in PCM systems having a free channel period, allocated, foriexample, for synchronizing purposes, can be carried out during that period. This is because during this period the encoder is not used and vcan be presented with a zero reference signal. Any output appearing during this period, therefore, indicates the presence of any offset, thusjpermitting a feedback correction mechanism to be emplfyed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an encoder system having a feedback control arrangement for centering of the input analog signal when no free period is available.

A feature of the present invention is the provision of an encoder system comprising an encoder to convert analog signals to successive code groups, each of the code groups having a polarity indicating digit and a plurality of digits representing the magnitude of an analog signal; iirst means coupled to the digital output of the encoder to examine the polarity of each of the code groups; second mear-s coupled to the first means to assign a polarity to a block of the code groups in accordance with the polarity distribution of each of the code groups in vthe block; and third means coupled to the second means and the analog input of the encoder responsive to the assigned polarity to equalize the number of the code groups in the block having opposite polarities.

EQZ Patented Feb. l0, 197@ .es l

e-ii

BRIEF DESCRIPTION OF THE DRAWING DESCRIPTION OF THE PREFERRED EMBODIMENTS A known control circuit for centering a symmetrical encoder is shown in FIG. 1. The encoder itself does not form part of the inveriftion and is indicated by the block 1. Any known type may be used provided it will encode an analog signal into asymmetrical binary code. An encoder of this type is described in my copending U.S. application, Ser. No. 652,053, filed July l0, 1967.

The automatic centering circuit of FIG. 1 comprises the feedback path connected between output circuit 2 of the encoder and the analog signal input circuit 3. The polarity digit of the coded output signal, or code group, is examined by logic AND gates 4 to which gating pulses are applied by conductor 5 from a timing generator (not shown). This gating pulse is time coincident with the polarity digit of each ot the code signals, or channel codes in a time division multiplex system. The output of the gate 4 is connected to bistable circuit 6. The arrangement is such that when the examined polarity digit of a code signal indicates a positive amplitude the bistable is in one condition and it changes over to the other condition when the polarity digit of a.; code signal indicates a negative amplitude. A square wave of constant amplitude will therefore appear at th-output of bistable circuit 6. The mark-space.ratio of this wave will depend on the ratio of positive and negativecode signals.

Since the analog signal to be encoded is an alternating current signal and hasftno D.C. component present, the ratio of positive and ngative going waves in a perfectly aligned encoder, when'examined over a suiciently long period of time, will be unity. The square wave is integrated in integrating network7 comprising capacitor C and resistor R. The analog output of the integrating network 7 is used to control bias, generator 8. The polarity of this bias is chosen to reduce the offset of the encoder.

The circuit of FIG.y 1 suffers from the disadvantage that if the time constant of the integrating circuit is short the assumption that there will be an equal number of positive and negative channels in a given period of time will not hold. A further disadvantage of the circuit is that the gain of the control loop, which can be defined as the change of the mark-space ratio of the signal at the output of bistable circuit 6 for a unit offset in the coded output signal at 2, decreases as the system loading is increased. By system loading is meant the product of the number of channels used and the amplitude of signal in each channel.

In order to demonstrate the dependence of the deviation of the mark/space ratio from unity on system loading, consider the case when all channels are equally loaded with maximum amplitude, i.e., the coder excursion is 2Q quantizing steps and that each level of each channel oc` curs with equal probability. Let p=probability of each channel code being positive; and q=probabi1ity of cach channel code being negative.

alittle Q Qmlwhich means that on the assumption that Q l the deviation of the ratio from unity is inversely proportional, to the number of levels excited.

The above expression is approximate only, since it does not take into account the fact that when the encoding characteristic is non-linear the effective number of linear levels may be very much greater than the actual, nonlinear levels. The assumption that all levels occur with equal probability is also an oversimpilication.

In order to combat this effect it is necessary to have a high gain in the control loop. This gain could be provided in the analogue part of the feedback path, i.e., after the integrating circuit. However, as it is necessary to limit the droop caused by the integrating network to a fraction of a quantum step, any gain inserted after the integrating network will amplify the droop unless the time constant of the integrating network is increased accordingly. Clearly, therefore, there is a practical limit to the gain that may be inserted after the integrating network i.e., in the analog part of the feedback circuit.

The gain of the feedback circuit can also be increased before the integrating network, i.e., in the digital part of the circuit. t

ln the arrangement according to FIG, 2, the error signal information derived from the inspection of the polarity digit of the successive channel codes appearing at the output of the encoder is fprocessed digitally and thereby amplified The terrn amplified must be taken to mean that for a given disparity between positive and negative channel codes the inclusion of digital processing into the feedback path will resultl in increasing the deviation from unity of the mark/space ratio of the signal appearing at the output from bistable unit 6.

The basic idea is to form groups of n channels and to assign to each group the polarity of the majority of channels in that group. This idea is carried into effect by including in the feedback path between the output from the encoder and the input to gates 4l bistable circuit counter 9 and an associated AND gate ttl which is controlled by a timing pulse applied to conductor lll. This L'ning pulse is generated by a timing generator (not own) to be time coincident with the polarity digit of 1.ach code signal, or channel code. The number of channels` of a given polarity is registered on the counter'D After the nal channel within the group has been inn spected, the counter register is examined by gates 4 activated by a timing pulse from a timing generator (not shown) succeeding the final channel of the group of channels, to see whether or not a count greater than one half the number of channels in the group of that polarity has been reached.. lf one half the count of counter 9 is .ceeded the last stage of counter 9 is n a ".l condition. n Athe other hand, the count is less than one half of the count the last stage of counter 9 is a O condition. lf this is tue rase bistable circuit xi is set to one stae, if not bistable is set to The other state. Th.: counter then reset o a pulse on conductor from a timing nera'tor (not shown). The outpuv from bistable 6 is .ippled to ir rating network l wluich serves the same junction as pre /iously described.

lt will now voe shown that the circuit according to FlG. 2 provides higher gain in the eedback path than the trirtlitotFIQf l; i

lll

l ln order to determine the mark/space ratio of bistable circuit o for a given offset in the encoder. it is necessary determine the probability ot a grotto o .mets having more positive than negative cha i codes in of the probability of each channel code within a group being positive. Since the polarity `of a group has been taken as that of the majority of channel codes within that group n is chosen to be an odd number.

The group will be positive if*` positive channels will be 2+ 1 i :pt igt 2 ).0 j

Similarly for case (2) the probability of there being positive channels will be Therefore, the probability pn of a `group of n channels having more positive channels than negative channels is given by il L1 @11:2( 2 2 2 m ne erp

Similarly the probability qn of the group having more negative than positive channels is given by n-l n+1 qnzp( 2 2 )UHC n l) Therefore, if the polarity of the groups are examined over a long .period of time the ratio of positive groups Le negative groups will be Dividing throughout by q there 1s obtained rl'his Value of pn/qn equals the average mark to space ratio of bistable circuit 6.

lf we designate by 51 the deviation from unity of the mark to space ratio of bistable circuit 6 in the arrangement of FIG. l for an j'offset of one quantum step and by 62 the deviation of the mark to space ratio for the arrangement according to FIG. 2, a comparison between the two circuits can be obtained by plotting 62 as a function of 51 for different vfalues of n. This is shown in FIG. 4 from which it is apparent that the gain of the feedback path increases witii` n, i.e., the number of channel codes per group. It will also be noted thatfwhen n is large the gain increases nir/ith the magnitude of the offset.

The gain of the feedback path can be increased still further by combining a'number m of groups of channel codes to a block of channel codes and allocating to the whole block the polarity,y of the majority of groups in the block. This is shown in the circuit of FIG. 3. A logic AND gate 13 and a counter 14 are added to the circuit of FIG. 2. Counter 14f`registers the number of groups within a block of channel codes having the given polarity and actuates bistable ciruit 6 when this number is greater than one-half of the total number of groups. If the number of counts is less than one-half, bistable 6 remains in its previous condition. When m groups have been examined counter 14 is reset by a timing pulse. The logic gate 13 is opened every time the store of counter 9 is examined, i.e., every time n channel codes have been ex amined. As before the tifrjning and reset pulses with appropriate timing for the gates 10, 13 and 4 and counters 9 and 14 are generated by a timing generator (not shown).

1. An encoder system comprising:

an encoder to convert analog signals to successive code groups, each of said code groups having a polarity indicating digit and a plurality of digits representing the magnitude of an analog signal;

first means coupled 'to the digital output of said encoder to examine the polarity of each of said code groups;

second means coupled to said first means to assign a polarity to a block of said code groups in accordance with the polarity distribution of each of said code groups in said block; and

third means coupled to said second means andfthe analog input of said encoder responsive to said assigned polarity to equalize the number of said code groups in said block having opposite polarities.

2. A system according to claim 1, wherein said' first means includes:

a gate circuit coupled to the digitaloutput of said encoder activated during time slots allocated to said polarity indicating digit of each of said code groups.

3. A system according to claim 1, wherein said sec= ond means includes:

a binary counter coupled to said first means to count the nurnber of said code groups having a given polarity.

l. A system according to claim 1, wherein said third means includes:

fourth means coupled to said second means to generate a digital control signal determined by the polarity o1? said block, fth means coupled to said fourth means to convert said control signal to an analog bias signal, and sixth means coupled to said iifth means and the analog input of said encoder responsive to said bias signal to equalize the number of said code groups in said block having opposite polarities.

. A system according to claim 1 said first means includesV v a gate circuit coupled to the digital output of said encoder activated during time slots allocated to said polarity indicating digit of 'i each of said code groups;

said second means includes v a binary counter coupled to said gate circuit to count the number of said code groups having a given polarity; and

said third means includes bistable means coupled to said binary counter set to one of its two conditions depending upon the polarity of said block to generate said control signal, f i

integrating means coupled to said bistable means to produce in response to said ontrol signal said bias signal, and y.

means coupled to said integrating means and the analog input of said encoder responsive to said bias signal to control the bias on said analog input of said encoder.

6. A system according tojclaim 1, wherein said block includes:

m groups of said code groups, each of said m groups including n of said code' groups, where m and n are odd integers; and

said second means assigns a polarity to each of said m groups determined by the polarity of a majority of said n of said codeN groups in each of said m groups and assigns a polarity to saidl block determined by the polarity of a majority of said m groups.

7. A system according to claim 6, wherein said rst means includes a gate circuit coupled to the digital output of said encoder activated during time slots allocated to said polarity indicating digit of each of said code groups.

8. A system according to claim 6, wherein said second means includes a first binary counter coupled to said first means to count the number of said n of said cod groups contained in each of said m groups having a given pou larity, and 'x a second binary counter coupled to said first binary counter to count the number of said ni groups havn ing a given polarity. E

9. A system according to claim 6, wherein said third means includes fourth means coupled to said second meai's to generate a digital control signal determined by 'tfiie polarity of said m groups, fifth means coupled to said fourth means to convert said control signal to an analog bias signal, and

sixth means coupled to said fifth means and the analog input of said encoder responsive to said bias signal to equalize the number of said m groups having opposite polarities.

10. A system according to claim 6, whizein said first means includes a gate circuit coupled to the digital output of said encoder activated during time slots allocated to said polarity indicating digit of each of said code groups;

said second means includes a rst binary counter coupled to said gate circuit to count the number of said n of said code groups contained in each of said m groups having a given polarity, and

a second binary counter coupled to said tirst binary counter to count the number of said m groups having a given polarity; and

said third means includes bistable means coupled to said second binary count wherein er" set to one o f its Fiwo comlitiens dependng References Ce pnlnrxly ot the majorxty of sand m UNH-ED STATES PATEN--S inregrting means coupled to sind bistable means 3548,03! 10/1967 Russen it tn prnduc in response 1G said control signal said 5 53492177 l0/1967 Cauermole 340-352 1 l y L mebalx; dclglen'; sad integrating means and the THOMAS A' ROBINSON prima, Examiner analog input of said encoder responsive to said bias :signin to control 'he bias on said analog inpui of said encoder,

US. Ci. 

